ECEA 5363 FPGA Capstone: Building FPGA Projects
4th course in the FPGA Design for Embedded Systems Specialization
Instructor: Timothy Scherr, MSEE, Senior Instructor
The objective of this course is provide a platform to get hands-on experience designing FPGA circuits and systems. To this end the DE10-Lite from TerAsic featuring the Intel Altera MAX10 FPGA is employed. The student will use this development kit to do a series of projects culminating in the construction of hardware and software for a System on a Chip (SoC) with the Nios II Soft Processor. All the prior lessons in this series of courses will be reinforced by the experience of building and testing real systems in the FPGA.
Prior knowledge needed: ECEA 5360 Introduction to FPGA Design for Embedded Systems, ECEA 5361 Hardware Description Languages for FPGA Design, ECEA 5362 FPGA Softcore Processors and IP Acquisition
Learning Outcomes
- Acquire an understanding of programmable systems on a chip for the purpose of creating prototypes or products for a variety of applications.
- Understand the use and proper application of Soft Processors for FPGAs.
- Create a Nios II Soft Processor, including both hardware and software design examples.
- Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging.
- Explore a number of example designs using FPGA development tools.
Syllabus
Duration: 10 hours
In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA.
Duration: 8 hours
The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument.
Duration: 8 hours
The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit.
Duration: 5 hours
The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well.
Duration: 2 hours
Final Exam for this course.
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Grading
Assignment | Percentage of Grade |
Module 1 Peer Review | 5% |
Module 1 Project Programming Assignment | 10% |
Module 1 Quiz | 5% |
Module 2 Peer Review | 5% |
Module 2 Project Programming Assignment | 10% |
Module 2 Quiz | 5% |
Module 3 Peer Review | 5% |
Module 3 Project Programming Assignment | 10% |
Module 3 Quiz | 5% |
Module 4 Peer Review | 5% |
Module 4 Project Programming Assignment | 10% |
Module 4 Quiz | 5% |
ECEA 5363 FPGA Capstone: Building FPGA Projects Final Exam | 20% |
Letter Grade Rubric
Letter Grade | Minimum Percentage |
A | 92% |
A- | 90% |
B+ | 87% |
B | 83% |
B- | 80% |
C+ | 77% |
C | 73% |
C- | 70% |
D+ | 67% |
D | 60% |
F | 0% |
Component List
- DE10-Lite Evaluation Board using the MAX 10 by Terasic Inc.
- You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, older ones may be upgraded.